A dual-NMOS power stage uses less power silicon area and provides faster switching than a PMOS power stage. A dual-NMOS power stage with an integrated charge pump has lower implementation cost and increased system reliability as compared with a bootstrap power stage requiring an external capacitor. The accumulation of full gate charge QG using a charge pump requires the same power as a bootstrap power stage. This power is VDD/VGS-times higher than the power required to accumulate gate charge corresponding to a gate voltage VGS from an ideal voltage source. However, beyond VDD/VGS, the implementation of a charge pump exhibits low power efficiency, which makes the gate charge transfer inefficient.